The present invention generally relates to analog-to-digital (A/D) converters, and more particularly to an A/D converter of the so-called sequential comparison type, for example, in which an input voltage is held using a sample and hold circuit and the input voltage is thereafter compared with a predetermined voltage.
FIG.1 shows an example of a conventional sequential comparison type A/D converter. A multiplexer 1 receives analog input signal (voltage) Al through An from a plurality of input channels, and selects one analog input signal in response to a channel selection signal CHS. A sample and hold (S/H) circuit 2 samples and holds the voltage of the output analog signal of the multiplexer 1 at a certain time. A comparator circuit 3 compares a voltage AN1 which is held in the S/H circuit 2 with an analog output voltage AN2 of a digital-to-analog (D/A) converter circuit 9. A control circuit 4 generates digital signals B1 through Bm corresponding to the voltage ANI which is held in the S/H circuit 2 based on a comparison result received from the comparator circuit 3. A sequential comparison register 5 temporarily stores the digital signals B1 through Bm output from the control circuit 4. An output storage register 6 stores the final result (digital signals Bl through Bm) of the contents of the sequential comparison register 5. The D/A converter circuit 9 generates the analog output voltage AN2 corresponding to the digital signals B1 through Bm stored in the sequential comparison register 5.
FIG.2 shows a conceivable construction of the A/D converter shown in FIG. 1. In FIG. 2, the same designations are used as in FIG.1. For the sake of convenience, it is assumed that the A/D converter shown in FIG.2 has three input channels ch1 through ch3, and that a 6-bit digital signal made up of bits B1 through B6 is output in response to an analog input signal.
The D/A converter circuit 9 includes a capacitor part 12 and a digital input part 14. The capacitor part 12 includes seven capacitors C1 through C6 and C6, and the capacitances of the capacitors C1, C2, C3, C4 and C5 respectively are 2.sup.5, 2.sup.4, 2.sup.3, 2.sup.2 and 2.sup.1 times the capacitance of the capacitor C6. The digital input part 14 makes charge and discharge operations with respect to electrodes X1 through X6 of the capacitors C1 through C6 based on digital control signals. The S/H circuit 2 includes a switch 15 and the capacitor part 12. In other words, the capacitor part 12 is used in common as a part of the D/A converter circuit 9 and a part of the S/H circuit 2. The comparator circuit 3 includes a comparator part 13 which is made up of comparators COM1 through COM3. The comparator COM1 includes an inverter IV1 and a transistor N7, the comparator COM2 includes an inverter IV2 and a transistor N8, and the comparator COM3 includes an inverter IV3 and a transistor N9 which are connected as shown. The comparators COM1 through COM3 are connected in series to obtain a relatively high amplification.
Next, a description will be given of an operation of the A/D converter shown in FIG.2 by referring to FIG.3.
First, a description will be given of the sampling and holding of the analog input signal which is to be compared.
(1) During a sampling time Ml in which a sampling pulse .phi..sub.SMP has a high level as shown in FIG.3(B), switches SW1 through SW3 of the multiplexer 1 are controlled based on the channel selection signal CHS. For example, the channel ch2 is selected from the input channels ch1 through ch3 in response to the channel selection signal CHS. The analog input signal of the input channel ch2 is 5V during the sampling time M1 as shown in FIG.3(A), and the voltage of 5V is applied in common to switches S1 through S6 of the switch 15 which correspond to the 6 bits. Since the switches S1 through S6 are closed during this sampling time Ml in response to a switching signal SWS, a charge corresponding to the voltage of the analog input signal is stored at the electrodes X1 through X6 of the capacitors C1 through C6 within the capacitor part 12. FIG.3(C) shows the voltage at the electrodes X1 through X6.
(2) The switches S1 through S6 are thereafter opened at an arbitrary time in response to the switching signal SWS, and this arbitrary time is the end of the sampling time M1 in this case. Hence, the charge corresponding to the voltage of the analog input signal is held at the electrodes Xl through X6 of the capacitors C1 through C6. In this state, high-level digital control signals D1a through D6a and low-level digital control signals D1b through D6b from the sequential comparison register 5 are supplied to the digital input part 14, but transistors P1 through P6 and N1 through N6 of the digital input part 14 are all OFF. Hence, the electrodes X1 through X6 are electrically isolated from the digital input part 14.
On the other hand, during the sampling time M1, a charge equal to the charge at the electrodes X1 through X6 but of the opposite polarity is stored at electrodes Y1 through Y6 because the transistors N7 through N9 of the comparator part 13 are ON. Since input and output ends of the inverter IV1 are short-circuited in this state, the voltage at the electrodes Y1 through Y6 is approximately the logic threshold voltage of the inverter IV1 which is 2.5 V, for example. At an arbitrary time, the negative charge of a quantity equal to the positive charge stored at the electrodes Xl through X6 is sampled and held at the electrodes Y1 through Y6.
Next, a description will be given of a first comparison of the analog input signal and the digital value received from the sequential comparison register 5.
(3) During a sequential comparison time ml in which the sampling pulse .phi..sub.SMP has a low level as shown in FIG.3(B), the transistors N7 through N9 of the comparator part 13 are OFF and the comparator part 13 is in a comparing mode.
The control circuit 4 sets "1" to only the most significant bit (MSB) B1 and sets the digital signals B1 through B6 ("100000") into the sequential comparison register 5. For example, the MSB B1 has a voltage which is 1/2 the sum of maximum and minimum voltages of the analog signal which is output from the D/A converter circuit 9. The sequential comparison register 5 transmits the digital signals B1 through B6 to the digital input part 14 by supplying high-level digital control signals D1a and D1b and low-level digital control signals D2a through D6a and D2b through D6b.
The transistors P1 through P6 and N1 through N6 of the digital input part 14 are controlled by the digital control signals D1a through D6a and D1b through D6b so that a positive charge is stored at only the electrode X1 of the capacitor Cl and the charge in the capacitors C2 through C6 are discharged by grounding the electrodes X2 through X6. Accordingly, a negative charge of a quantity equal to the positive charge stored at the electrode X1 is stored at the other electrode Y1 of the capacitor C1. However, the total charge stored at the electrodes Y1 through Y6 during the sampling (2) described above is greater than the total charge stored at the electrodes X1 through X6, and the voltage at the electrode Y6 decreases. The gate voltage at the inverter IV1 of the comparator part 13 becomes smaller than the threshold voltage during the sampling time Ml, and a transistor P10 of the inverter IV1 turns ON to supply a comparison result REFS which is "1" to the control circuit 4. The transistor P10 forms the inverter IV1 together with a transistor N10.
Next, a description will be given of a second comparison of the analog input signal and the digital value received from the sequential comparison register 5.
(4) When the comparison result REFS is "1" as a result of the comparison (3) described above, the control circuit 4 sets the second MSB B2 to "1", and supplies the digital signals B1 through B6 ("110000" to the sequential comparison register 5. For example, the second MSB B2 has a voltage which is 3/4 the sum of maximum and minimum voltages of the analog signal which is output from the D/A converter circuit 9.
On the other hand, when the comparison result REFS is "0" as a result of the comparison (3) described above, the control circuit 4 sets the MSB B1 to "0" and the second MSB B2 to "1", and supplies the digital signals B1 through B6 ("010000") to the sequential comparison register 5. For example, the second MSB B2 has a voltage which is 1/4 the sum of maximum and minimum voltages of the analog signal which is output from the D/A converter circuit 9.
The digital input part 14 supplies charges corresponding to the digital signals B1 through B6 to the respective electrodes X1 through X6 of the capacitors C1 through C6. Accordingly, a negative charge of a quantity equal to the total charge stored at the electrodes X1 and X2 is stored at the electrode Y1, and the total charge stored at the electrodes Y1 through Y6 raises or lowers the voltage at the electrodes Y1 through Y6 depending on the relationship with the total charge stored at the electrodes X1 through X6. The comparator part 13 supplies the comparison result REFS to the control circuit 4 based on the relationship of the voltage at the electrodes Y1 through Y6 and the threshold voltage of the inverter IV1.
Next, a description will be given of third through sixth comparisons of the analog input signal and the digital value received from the sequential comparison register 5.
(5) The comparison is repeated for 3, 4, 5 and 6 bits based on the comparison result REFS from the comparator part 3, similarly as in the case of the operations (3) and (4) described above. When six comparisons to a least significant bit (LSB) B6 ends, the control circuit 4 stores the digital signals B1 through B6 at the time when the comparison ends into the output storage register 6 via the sequential comparison register 5. For example, the digital signals B1 through B6 which are stored in the output storage register 6 are used as data of a microcomputer (not shown).
(6) At the next A/D conversion cycle, the operations (1) through (5) described above are repeated so as to carry out a continuous A/D conversion.
For example, the sequential comparison type A/D converter described above is provided on a single chip together with a microprocessor, and is used for converting analog signals from various sensors such as temperature and flow rate sensors into digital signals when carrying out a process such as temperature control and flow rate control. In the case shown in FIG.2, a sensor 10 detects a change in external temperature or flow rate and outputs an analog signal which describes the detection result. This analog signal from the sensor 10 is supplied to the multiplexer 1 of the A/D converter.
However, the analog signal from the sensor 10 includes a small noise component in addition to the effective signal component. For this reason, a filter is provided inside the sensor 10 or connected externally to the sensor 10 so as to eliminate the noise component. In the case shown in FIG.2, the filter is made up of a capacitor C.sub.S and a resistor R.sub.S which are connected in parallel, and this filter is connected to an internal circuit 11 of the sensor 10.
When the noise component output from the sensor is relatively large, the capacitance of the capacitor C.sub.S and the resistance of the resistor R.sub.S are respectively set large in order to eliminate the noise component. For example, the capacitance of the capacitor C.sub.S is set to 10 .mu.F and the resistance of the resistor R.sub.S is set to 10 k.OMEGA..
However, when the analog signal from the sensor includes the relatively large noise component, the charge which is held in the S/H circuit 2 during the Nth A/D conversion cycle of the sequential comparison type A/D converter may not change quickly enough to the charge which corresponds to the analog input signal which is to be held during the (N+1)th A/D conversion cycle because of the large difference in the voltages held in the S/H circuit 2 during the Nth and (N+1)th A/D conversion cycles.
The above described problem will now be described in more detailed by referring to FIG.3. For the sake of convenience, it is assumed that during the Nth A/D conversion cycle which includes the sampling time M1 and the sequential comparison time ml, the analog input signal is 5 V which is the maximum value of the input analog signal of the sequential comparison type A/D converter as shown in FIG.3(A) and the charge corresponding to this 5 V is held at the capacitor part 12 during the sampling time Ml by the operation (2) described above. In this case, the same charge is stored at the electrodes Y1 through Y6 of the capacitors C1 through C6. The held charge is used to generate the digital signal corresponding to the 5 V analog input signal during the sequential comparison time ml by the operations (3) through (5) described above. When the operation (5) ends during the sequential comparison time ml, that is, at the end of the sixth comparison described above, a charge approximately equal to the 5 V held in the capacitor part 12 is held at the electrodes X1 through X6 of the capacitors C1 through C6 by the sequential comparison.
As shown in FIG.3(A), during the next (N+l)th A/D conversion cycle which includes a sampling time M2 and a sequential comparison time m2, it is assumed for the sake of convenience that the analog input signal is 0 V which is the minimum value of the input analog signal of the sequential comparison type A/D converter. In this case, during the sampling time M2, the digital input part 14 is electrically isolated from the capacitors C1 through C6, and the charge at the electrodes X1 through X6 is discharged towards the sensor 10 when the switches S1 through S6 close. However, since the capacitance and the resistance of the respective capacitor C.sub.S and the resistor R.sub.S are large, this discharge is suppressed.
For this reason, when the sampling time M2 shown in FIG.3(C) is short, the sampling time M2 ends before the voltage at the electrodes X1 through X6 fall to 0 V. In this case, a voltage which is .phi. V greater than 0 V is erroneously held at the electrodes X1 through X6. A similar situation occurs when the analog input signal is 0 V during the Nth A/D conversion cycle and the analog input signal is 5 V during the next (N+1)th A/D conversion cycle. In this latter case, the sampling time M2 ends before the voltage at the electrodes X1 through X6 rise to 5 V.
On the other hand, if the sampling times M1, M2, . . . , Mn were respectively made sufficiently long, the .phi. V is gradually discharged via the capacitor C.sub.S and the resistor R.sub.S, and thus, the voltage at the electrodes X1 through X6 fall to approximately 0 V. But this would inevitably require long A/D conversion cycles, thereby making a high-speed A/D conversion difficult.